The present invention relates to a data transfer control device and an electronic instrument.
In recent years, a high-speed serial transfer interface such as low voltage differential signaling (LVDS) has attracted attention as an interface aiming at reducing EMI noise or the like. In such a high-speed serial transfer, data transfer is realized by causing a transmitter circuit to transmit serialized data using differential signals and a receiver circuit to differentially amplify the differential signals. The Digital Visual Interface (DVI) or the like has been known as an interface for such a high-speed serial transfer.
An ordinary portable telephone includes a first instrument section provided with buttons for inputting a telephone number or a character, a second instrument section provided with a main liquid crystal display (LCD), a sub LCD, or a camera, and a connection section such as a hinge which connects the first and second instrument sections. In this case, the number of interconnects passing through the connection section can be reduced by performing data transfer between a first substrate provided in the first instrument section and a second substrate provided in the second instrument section by serial transfer using differential signals.
However, when performing data transfer through such a connection section by serial transfer, it is desirable to reduce power consumption of a host-side data transfer control device and a target-side data transfer control device which control the serial transfer. It is also desirable to reduce the amount of data transferred through the serial bus. Furthermore, it is desirable to reduce the processing load imposed on a system device (CPU, display controller, or the like) which accesses the host-side data transfer control device and performs various settings.
When the system device outputs an RGB interface synchronization signal to the host-side data transfer control device, it is desirable that the target-side data transfer control device reproduce the synchronization signal using simple processing and output the synchronization signal to a device connected to the interface bus.